(1) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and a test method for the same. Further, the invention relates to a semiconductor memory having a sense amplifier, and a semiconductor device. More particularly, the invention relates to a semiconductor device and a test method for the same, wherein testing can be conducted easily to check whether the fabricated semiconductor device has a prescribed performance.
(2) Description of the Related Art
Semiconductor memories such as DRAM and SRAM are widely used, and flash memory has been attracting attention as an electrically erasable nonvolatile memory. Each memory cell of a flash memory consists of a single transistor. This transistor is called a memory cell transistor. A memory cell transistor of the flash memory has the structure of an n-channel MOS transistor with a floating gate formed beneath its gate. For erasure, a control gate is left open, and a high voltage is applied to a source, which causes a charge to be drawn through the source, leaving almost zero charge on the floating gate. In this situation, when an appropriate voltage is applied to the control gate, the transistor conducts. When a high voltage is applied to the control gate and the drain, avalanche breakdown occurs, and part of electrons that have gained high energy near the drain are captured by the floating gate. This operation is called writing. Once writing is done, the charge remains accumulated on the floating gate, so that the transistor will not conduct even when a voltage is applied to the control gate. Data is defined according to whether the transistor conducts or not. In the flash memory, the writing and erasure of information can be accomplished electrically, as described above.
Flash memories require different voltages for different operating modes, read, write, and erasure, for application to various elements, and accordingly, their control operations are complex: Furthermore, a read or erase operation is usually followed by a verify operation to verify the processed data by reading it. Such operations have previously been done by applying prescribed voltages to designated terminals of the flash memory by using a writer or other external equipment. This puts a great deal of load on the writer and other external equipment used for write and erase operations.
To simplify such complex control algorithms, the recent flash memory design incorporates automatic circuitry that allows the writing and erasure of flash memory cells to be accomplished just by entering simple control commands from the outside. Such a flash memory design is becoming predominant.
In a flash memory equipped with such automatic circuitry, once an external control command is accepted, all processing is automatically done internally until a cell write or erase operation is completed. It is therefore usual to provide a status register facility as a means for allowing external monitoring of the device status.
Once the automatic circuitry is activated, it is not possible to know the status of internal circuitry without reading out the status register.
After the fabrication of a semiconductor device is completed, various tests are performed to check whether the semiconductor device has the prescribed performance.
In the case of a nonvolatile memory such as a flash memory, for example, a test is performed to check whether the status register functions properly. The status register provides an external indication of the status of write and erase operations performed by the operational logic circuit; that is, the bit values in the status register indicate whether the write or erase operation has been completed correctly. Therefore, to verify whether the status register is functioning correctly, the operational logic circuit is actually made to perform various operations to produce various status conditions, and the status register is tested to see whether it reflects the status correctly.
In the status register test procedure above, only the operation of the status register is tested. For example, when the operation of the status register for write mode is tested, the test result of normal or failure is set into the status register without performing real write and verify operations. Therefore, the procedure does not guarantee that the status register 2 will function properly when a failure occurs in the memory cell matrix or a sense amplifier/write amplifier.
Namely, with the status register test for a flash memory explained above, it is only possible to verify the status register function and part of the whole circuit operation.
In the testing of memories, with increasing memory capacity, the test time is increasing by a large extent, which pushes the test costs even higher than before. To reduce the test costs, it is important to be able to identify defects in the shortest possible time, but at the same time, it is also important to combine various tests into a single comprehensive test process to reduce the test time and minimize the increase in test costs. Therefore, in the status register test also, it is desirable that the test be performed in a more comprehensive manner, not limiting the test to the parts mentioned above. The test method currently practiced is not sufficient from this point of view.
Among tests unique to a nonvolatile memory such as a flash memory, there is a test to guarantee proper retention of the stored data for long periods of time after power to the memory is removed. Since such a long-period test cannot be performed under actual conditions, the data retention test is usually conducted by an accelerated test called an aging test. In the aging test, after writing is done up to a prescribed level, accelerating stresses are applied to stress the data retention conditions by holding the device at a temperature higher than normal, and after that, the threshold level is detected.
As described above, each individual device is subjected to the aging test after it is assembled and sealed in a package.
However, since the aging test as described above is performed in the final test step after the device assembly, a sufficiently high temperature cannot be applied to the device assembled in a plastic package, thus requiring a long aging time to guarantee the reliability of data retention, and hence increasing the number of steps.
There has been proposed another process different from the above process in which the aging test is performed between a passivation layer growing step and the coating film growing step. In this process, after writing is done up to a prescribed level, accelerating stresses are applied in the aging step where the device is held for one hour at 300.degree. C. Then, the data level is verified.
With the aging test described above, while it can guarantee the device reliability since the devices are subjected to aging on the wafer, it still involves a problem in that it increases the number of steps.
Furthermore, for a semiconductor memory, a power supply margin on the high-voltage side that can be applied to the memory cell needs to be measured. However, the memory cell current characteristic is such that the gradient decreases with increasing gate voltage; therefore, the sense amplifier of the prior art has the problem that the sense point becomes displaced when the supply voltage is increased, which prevents correct cell comparison. To avoid this problem, an extra circuit has to be added so that the sense amplifier power supply can be separated from the cell power supply, and also, a special test for measuring it has to be added.
When measuring the power supply margin for the sense amplifier, the test is performed using a circuit that separates the sense amplifier power supply from the cell gate power supply. Such a test, however, cannot be performed in the usual test process, but a separate test step for that purpose needs to be provided. The problem here is that the extra test in addition to the usual test steps will introduce an extra cost which will be reflected in the final chip cost.
Furthermore, for a semiconductor device, the power supply current during operation needs to be measured. Because of the test process employed, the power supply current is measured using a setup with the output pin connected to a load circuit. The measuring conditions for the operating power supply current guaranteed in specifications, etc., require that the current flowing through a load be 0 mA. However, when the measurement is made with the output connected to the load circuit, the correct current value cannot be obtained since the charge/discharge current flowing through the load circuit is also measured. Therefore, when measuring the guaranteed design value, the output pin is disconnected from the measuring circuit.
With the output circuit setup described above, the power supply current cannot be accurately measured; therefore, the measurement is made after disconnecting the output pin from the measuring circuit. This introduces a cumbersome step in the test process.